The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Oct. 26, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Wolfgang Gellerich, Boeblingen, DE;

Peter M. Held, Renningen, DE;

Gerrit Koch, Ammerbuch, DE;

Martin Schwidefsky, Boeblingen, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); G06F 9/00 (2006.01); G06F 9/44 (2018.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3844 (2013.01); G06F 9/3012 (2013.01); G06F 9/30047 (2013.01); G06F 9/30058 (2013.01);
Abstract

Examples of techniques for branch prediction for indirect branch instructions are described herein. An aspect includes detecting a first register setting instruction in an instruction pipeline of a processor, wherein the first register setting instruction stores a target instruction address in a first register of the processor. Another aspect includes looking up the first register setting instruction in a first table. Another aspect includes, based on there being a hit for the first register setting instruction in the first table, determining instruction address data corresponding to a first indirect branch instruction that is associated with the first register setting instruction in a first entry in the first table. Another aspect includes updating a branch prediction for the first indirect branch instruction in a branch prediction logic of the processor based on the target instruction address.


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