The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Oct. 10, 2017
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Shintaro Harada, Kanagawa, JP;

Yoshiyuki Kurokawa, Kanagawa, JP;

Takeshi Aoki, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/544 (2006.01); G06N 3/063 (2006.01); H01L 29/786 (2006.01); G06N 3/04 (2006.01);
U.S. Cl.
CPC ...
G06F 7/5443 (2013.01); G06N 3/04 (2013.01); G06N 3/0635 (2013.01); H01L 29/7869 (2013.01);
Abstract

A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor. A voltage between the first terminal and the second gate of the transistor is held in the capacitor, whereby a change in source-drain current of the transistor can be suppressed.


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