The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Dec. 21, 2019
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Seon Ju Lee, Seongnam-si, KR;

Min Hwan Moon, Seoul, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/064 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01); G11C 16/349 (2013.01); G11C 29/52 (2013.01);
Abstract

A memory controller having improved wear-leveling performance controls a memory device including a plurality of memory blocks. The memory controller includes a read operation controller, a cell state determiner, and a read reclaim controller. The read operation controller controls the memory device to read selected memory cells of a first block among the plurality of memory blocks by using at least one reference voltage. The cell state determiner compares a number of memory cells among the selected memory cells that are read as first memory cell with a reference number corresponding to the at least one reference voltage, and generates cell state information indicating a memory cell degradation degree corresponding to at least one state. The read claim controller controls the memory device to copy data stored in the first block to a second block, based on a comparison between the memory cell degradation degree with a threshold degradation degree.


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