The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Oct. 28, 2019
Applicant:

Maxlinear, Inc., Carlsbad, CA (US);

Inventors:

Curtis Ling, Carlsbad, CA (US);

Shantha Murthy Prem Swaroop, Carlsbad, CA (US);

Vinit Jayaraj, Carlsbad, CA (US);

Assignee:

MaxLinear, Inc., Carlsbad, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 3/156 (2006.01); H03M 1/14 (2006.01);
U.S. Cl.
CPC ...
H02M 3/1584 (2013.01); H02M 3/156 (2013.01); H02M 2003/1586 (2013.01); H03M 1/143 (2013.01);
Abstract

Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output DC voltage with controlled ripple current. The buck converter may include one or more main buck converter stages with coupled outputs and one or more harmonic suppression buck converter stages in parallel with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents at the coupled outputs to cancel ripple currents generated in the one or main buck converter stages. Each of the one or more main buck converter stages and each of the one or more suppression buck converter stages may include a stacked transistor pair with an inductor at an output. A drain terminal of one transistor of each transistor pair in the one or more main buck converter stages may be biased at a first supply voltage.


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