The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Mar. 26, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Benjamin Wunsch, Mt. Kisco, NY (US);

Joshua T. Smith, Croton on Hudson, NY (US);

Stacey Gifford, Fairfield, CT (US);

Michael Albert Pereira, Westchester, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/04 (2014.01); G01N 33/487 (2006.01); G01N 33/50 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); G01N 33/48707 (2013.01); G01N 33/50 (2013.01); H01L 24/05 (2013.01); H01L 24/94 (2013.01); H01L 25/042 (2013.01); H01L 25/0657 (2013.01); H01L 2224/05 (2013.01); H01L 2224/94 (2013.01); H01L 2924/06 (2013.01); H01L 2924/10253 (2013.01);
Abstract

A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.


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