The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2021
Filed:
Sep. 27, 2019
Applicant:
Nanya Technology Corporation, New Taipei, TW;
Inventor:
Chih-Tsung Wu, Taoyuan, TW;
Assignee:
NANYA TECHNOLOGY CORPORATION, New Taipei, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 27/108 (2006.01); H01L 23/528 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53295 (2013.01); H01L 21/02164 (2013.01); H01L 21/31116 (2013.01); H01L 21/7682 (2013.01); H01L 21/76802 (2013.01); H01L 21/76837 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 27/10814 (2013.01); H01L 27/10885 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 27/10823 (2013.01); H01L 27/10888 (2013.01); H01L 27/10891 (2013.01);
Abstract
The present disclosure provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a plurality of spacer bit lines disposed over a substrate; a plurality of dielectric pillars disposed over the substrate, between the plurality of spacer bit lines; and a sealing dielectric layer disposed over the plurality of spacer bit lines and the plurality of dielectric pillars such that air gaps are formed between the sealing dielectric layer and the substrate.