The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Feb. 22, 2018
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Shinichi Miyake, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/60 (2006.01); H01L 21/3205 (2006.01); H01L 21/3065 (2006.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3205 (2013.01); H01L 21/3065 (2013.01); H01L 21/768 (2013.01); H01L 21/822 (2013.01); H01L 23/522 (2013.01); H01L 23/60 (2013.01); H01L 27/0255 (2013.01); H01L 27/0629 (2013.01);
Abstract

The present technology relates to a semiconductor device and a manufacturing method that make it possible to reduce PID. The semiconductor device includes a first layer, a second layer laminated with the first layer, a conductive member that comes into contact with a lateral surface of a groove part formed in the first layer and the second layer, and first wiring that is formed in the second layer and comes into contact with a bottom surface of the groove part. The conductive member is connected to a protecting element for discharging charges accumulated inside the groove part. The present technology is applicable to, for example, the formation of a via in a silicon substrate and an interlayer film laminated with each other.


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