The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Jun. 06, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Manoj Dusanapudi, Bangalore, IN;

Shakti Kapoor, Austin, TX (US);

Nelson Wu, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/38 (2006.01); G11C 29/36 (2006.01); G11C 29/50 (2006.01); G11C 29/44 (2006.01); G11C 29/06 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 29/36 (2013.01); G11C 29/50 (2013.01); G11C 29/06 (2013.01); G11C 2029/4402 (2013.01);
Abstract

A processor memory is stress tested with a variable list insertion depth using list insertion test segments with non-naturally aligned data boundaries. List insertion test segments are interspersed into test code of a processor memory tests to change the list insertion depth without changing results of the test code. The list insertion test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The list insertion test segments include list insertion segments and load/store segments. The list insertion segments locate a current memory location using a fixed segment at a known location. The load/store segments load and store list elements in memory.


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