The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2021
Filed:
May. 27, 2020
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Sung Lae Oh, Cheongju-si, KR;
Dong Hyuk Kim, Seoul, KR;
Tae Sung Park, Icheon-si, KR;
Soo Nam Jung, Seoul, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 16/24 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 27/11565 (2017.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract
A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions.