logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11094355 B1

PDFFull Text
Date of Patent:
Aug. 17, 2021

Filed:

May. 05, 2020

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

Applicant:

Ecole Polytechnique Federale DE Lausanne (Epfl), Lausanne, CH;

Inventors:

William Andrew Simon, Prilly, CH;

Marco Antonio Rios, Chavannes-Renens, CH;

Alexandre Sébastien Levisse, Lausanne, CH;

Marina Zapater, Chavannes-Renens, CH;

David Atienza Alonso, Echandens-Denges, CH;

Assignee:

ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL), Lausanne, CH;

Attorneys:

Andre Roland S.A.

Nikolaus Schibli

Primary Examiner:

Xiaochun L Chen

Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 7/10 (2006.01); G11C 7/14 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/065 (2013.01); G11C 7/106 (2013.01); G11C 7/1012 (2013.01); G11C 7/1027 (2013.01); G11C 7/1087 (2013.01); G11C 7/14 (2013.01);
Abstract

A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a pair of global read bitlines, a local group read port arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell, and a local group precharge circuit operatively arranged between the pair of local bitlines.

Find Patent Forward Citations

Simon, William. (2021). Memory chip or memory array for wide-voltage range in-memory computing using bitline technology (U.S. Patent No. 11094355). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11094355

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…