The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Jun. 17, 2020
Applicant:

Shanghaitech University, Shanghai, CN;

Inventors:

Xinzhe Liu, Shanghai, CN;

Fupeng Chen, Shanghai, CN;

Yajun Ha, Shanghai, CN;

Assignee:

SHANGHAITECH UNIVERSITY, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/44 (2017.01); G06F 9/38 (2018.01); G06F 1/10 (2006.01); G06F 9/30 (2018.01); G06F 9/54 (2006.01);
U.S. Cl.
CPC ...
G06T 7/44 (2017.01); G06F 1/10 (2013.01); G06F 9/30109 (2013.01); G06F 9/3838 (2013.01); G06F 9/545 (2013.01);
Abstract

An efficient parallel computing method for a box filter, includes: step 1, with respect to a given degree of parallelism N and a radius r of the filter kernel, establishing a first architecture provided without an extra register and a second architecture provided with the extra register; step 2, building a first adder tree for the first architecture and a second adder tree for the second architecture, respectively; step 3, searching the first adder tree and the second adder tree from top to bottom, calculating the pixel average corresponding to each filter kernel by using the first adder tree and the second adder tree, respectively, and counting resources required to be consumed by the first architecture and the second architecture, respectively; and, step 4, selecting one architecture consuming a relatively small resources from the first architecture and the second architecture for computing the box filter.


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