The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Sep. 25, 2019
Applicant:

Vmware, Inc., Palo Alto, CA (US);

Inventors:

Benjamin C. Serebrin, Sunnyvale, CA (US);

Bhavesh Mehta, Sunnyvale, CA (US);

Assignee:

VMware, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1036 (2016.01); G06F 12/10 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1036 (2013.01); G06F 12/10 (2013.01);
Abstract

In a computer system having virtual machines, one or more unused bits of a guest physical address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2)-th of a memory page.


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Serebrin, Benjamin. (2021). Increasing granularity of dirty bit information in hardware assisted memory management systems (U.S. Patent No. 11093407). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11093407

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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