Performant inline ecc architecture for dram controller

Abstract

Techniques are disclosed for reducing the time required to read and write data to memory. Data reads and/or writes can be delayed when error correction code (ECC) bits, which are used to detect and/or correct data corruption, are written to memory. Writing ECC bits can take longer in some instances than writing data bits because an ECC write may involve a read/modify/write operation, as opposed to just simply writing the bits to memory. Some latencies associated with writing ECC bits can be hidden by interleaving ECC writes with data writes. However, if insufficient data writes are available for interleaving, hiding such latencies become difficult. Thus, various techniques are disclosed, for example, where ECC writes are deferred until a sufficient number of data writes become available for interleaving. By interleaving ECC writes, the disclosed techniques decrease the overall time required to read and write data to memory.