The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11093224 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 17, 2021

Filed:

Apr. 24, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Eri Ogawa, Saitama-ken, JP;

Kazuaki Ishizaki, Tokyo, JP;

Hiroshi Inoue, Tokyo, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 8/41 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 8/41 (2013.01); G06F 8/443 (2013.01); G06F 8/447 (2013.01); G06F 8/452 (2013.01); G06F 9/30058 (2013.01); G06F 9/30065 (2013.01);
Abstract

A method performed during execution of a compilation process for a program having nested loops is provided. The method replaces multiple conditional branch instructions for a processor which uses a conditional branch instruction limited to only comparing a value of a general register with a value of a special register that holds a loop counter value. The method generates, in replacement of the multiple conditional branch instructions, the conditional branch instruction limited to only comparing the value of the general register with the value of the special register that holds the loop counter value for the inner-most loop. The method adds (i) a register initialization outside the nested loops and (ii) a register value adjustment to the inner-most loop. The method defines the value for the general register for the register initialization and conditions for the generated conditional branch instruction, responsive to requirements of the multiple conditional branch instructions.


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Ogawa, Eri. (2021). Compilation to reduce number of instructions for deep learning processor (U.S. Patent No. 11093224). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11093224

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