The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Oct. 13, 2020
Applicant:

Ningbo University, Zhejiang, CN;

Inventors:

Pengjun Wang, Zhejiang, CN;

Xiaotian Zhang, Zhejiang, CN;

Huihong Zhang, Zhejiang, CN;

Yuejun Zhang, Zhejiang, CN;

Haizhen Yu, Zhejiang, CN;

Assignee:

Ningbo University, Zhejiang, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/507 (2006.01); H03K 19/003 (2006.01); H03K 19/0948 (2006.01);
U.S. Cl.
CPC ...
G06F 7/507 (2013.01); H03K 19/00323 (2013.01); H03K 19/0948 (2013.01);
Abstract

A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.


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