The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Oct. 21, 2020
Applicant:

Siliconch Systems Pvt Ltd, Karnataka, IN;

Inventors:

Sabu Paul, Karnataka, IN;

Rohit Dawar, Karnataka, IN;

Nitish Kuttan, Karnataka, IN;

Ch Yaswanth Sai Kiran, Andhra Pradesh, IN;

Assignee:

SILICONCH SYSTEMS PVT LTD, Karnataka, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/00 (2006.01); H03M 1/08 (2006.01); H03M 1/18 (2006.01); H03M 1/06 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1245 (2013.01); H03M 1/001 (2013.01); H03M 1/0607 (2013.01); H03M 1/0872 (2013.01); H03M 1/181 (2013.01);
Abstract

The present disclosure provides an analogue to digital converter (ADC) (), which includes: a capacitive digital to analogue converter (DAC) () configured to sample and hold a received sampling input signal and a latched comparator () including a first metal oxide semiconductor field effect transistor (MOSFET) (); a second MOSFET () connected in parallel to the first MOSFET; a third MOSFET (), wherein a third source terminal of the third MOSFET () is coupled with first drain terminal and second drain terminal of the first and second MOSFET (), wherein a sampling switch () is configured to the third source terminal to selectively allow voltage to be supplied to the third MOSFET (), and wherein the sampling switch is configured to disallow voltage to be supplied to the third MOSFET when the ADC is sampling the input signal.


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