The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Mar. 04, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventor:

Yuki Kasai, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4234 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02167 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01); H01L 29/40117 (2019.08); H01L 29/512 (2013.01); H01L 29/518 (2013.01);
Abstract

An alternating stack of insulating layers and spacer material layers is formed located over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack. A memory stack structure is formed within each memory opening. Each memory stack structure includes a memory film and a vertical semiconductor channel. A silicon nitride layer is formed over a sidewall of each memory opening as a component of the memory film. A silicon carbon nitride interfacial layer is formed on the silicon nitride layer, and a tunneling dielectric layer is formed on the silicon carbon nitride interfacial layer.


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