The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Aug. 30, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventor:

Kojiro Shimizu, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 23/52 (2006.01); H01L 27/11582 (2017.01); H01L 23/528 (2006.01); H01L 27/11565 (2017.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/528 (2013.01); H01L 21/0274 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 27/11565 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: first interconnect layers; a second interconnect layer separate from the first interconnect layers; a third interconnect layer separate from the first interconnect layers and adjacent to the second interconnect layer in a second direction; a first memory pillar which passes through the second interconnect layer; a second memory pillar which passes through the third interconnect layer. The second interconnect layer includes a first portion connected to a first contact plug. The third interconnect layer includes a second portion connected to a second contact plug. The first and second portions are arranged along a third direction which intersects the second direction.


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