The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Feb. 25, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Kotaro Fujii, Yokkaichi, JP;

Satoshi Nagashima, Yokkaichi, JP;

Yumi Nakajima, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 21/8234 (2006.01); G11C 16/04 (2006.01); H01L 27/1157 (2017.01); H01L 27/11524 (2017.01); H01L 27/11565 (2017.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/0483 (2013.01); H01L 21/823487 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); H01L 27/11519 (2013.01); H01L 27/11565 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a first insulating layer provided between first and second interconnection layers; a first semiconductor layer provided between the first interconnection layer and the first insulating layer; a second semiconductor layer provided between the second interconnection layer and the first insulating layer; a first charge storage layer provided between the first interconnection layer and the first semiconductor layer; a second charge storage layer provided between the second interconnection layer and the second semiconductor layer; and a second insulating layer provided between the first interconnection layer and the second interconnection layer, between the first semiconductor layer and the second semiconductor layer, and between the first charge storage layer and the second charge storage layer.


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