The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Dec. 27, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventor:

Teruo Okina, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 23/532 (2006.01); H01L 27/11582 (2017.01); H01L 23/522 (2006.01); H01L 27/1157 (2017.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/76843 (2013.01); H01L 21/76852 (2013.01); H01L 21/76865 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 23/53295 (2013.01); H01L 24/06 (2013.01); H01L 24/09 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80357 (2013.01); H01L 2224/80895 (2013.01);
Abstract

A semiconductor die includes at least one first semiconductor device located on a first substrate, a first pad-level dielectric layer which is a diffusion barrier overlying the at least one first semiconductor device, and first bonding structures including a respective first metallic bonding pad embedded in the first pad-level dielectric layer. Each of the first bonding structures includes a metallic fill material portion having a horizontal distal surface that is located within a horizontal plane including a horizontal distal surface of the first pad-level dielectric layer, and a metallic liner laterally surrounding the metallic fill material portion and vertically spaced from the horizontal plane by a vertical recess distance.


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