The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Feb. 05, 2020
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Yoshinori Matsuno, Tokyo, JP;

Toshikazu Tanioka, Tokyo, JP;

Yasunori Oritsuki, Tokyo, JP;

Kenichi Hamano, Tokyo, JP;

Naochika Hanano, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 29/78 (2006.01); H01L 23/532 (2006.01); H01L 23/34 (2006.01); H01L 23/485 (2006.01); H01L 29/20 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 23/34 (2013.01); H01L 23/485 (2013.01); H01L 23/53271 (2013.01); H01L 29/7815 (2013.01); H01L 29/1602 (2013.01); H01L 29/1608 (2013.01); H01L 29/2003 (2013.01);
Abstract

In some examples, a semiconductor device includes a substrate, an interlayer insulating film, a gate pad provided on the interlayer insulating film, a source electrode that is provided on the interlayer insulating film, source wiring provided on the interlayer insulating film, and gate wiring that is provided on the interlayer insulating film and is electrically connected to the gate pad. The size of the source wiring is not increased, and a high impurity concentration region having a higher impurity concentration than a drift layer is formed on the surface of the substrate at a location directly below the gate pad.


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