The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Dec. 11, 2018
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, CN;

Inventor:

Xiaodi Liu, Shenzhen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/033 (2006.01); H01L 27/12 (2006.01); H01L 21/308 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01); H01L 21/4763 (2006.01); H01L 21/467 (2006.01); H01L 21/4757 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0337 (2013.01); H01L 21/033 (2013.01); H01L 21/0334 (2013.01); H01L 21/0338 (2013.01); H01L 21/3088 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1288 (2013.01); H01L 21/3065 (2013.01); H01L 21/3086 (2013.01); H01L 21/31138 (2013.01); H01L 21/32134 (2013.01); H01L 21/32139 (2013.01); H01L 21/467 (2013.01); H01L 21/47573 (2013.01); H01L 21/47635 (2013.01); H01L 27/1225 (2013.01);
Abstract

The invention provides a manufacturing method of the TFT array substrate. Compared to existing 4M process, the invention changes the structural design of the semi-transmissive mask for the photoresist layer for patterning the source/drain metal layer and the semiconductor layer. The edge forms a reduced thickness edge portion, so that the edge of the photoresist layer is thinned, and thereby the width of the photoresist layer is easily reduced in subsequent processes, and the semiconductor layer at the edge of the metal wire structure is easily etched during dry etching, reducing the tailing problem of the active layer at edges of source/drain to achieve finer metal wire structure, and improve optical stability, electrical performance, aperture ratio, reliability, power consumption, and the overall performance of the TFT array substrate. The residual problem of amorphous and heavily doped silicon on source/drain edge in original process is solved or reduced.


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