The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Dec. 12, 2019
Applicants:

SK Hynix Inc., Icheon, KR;

Seoul National University R&db Foundation, Seoul, KR;

Inventors:

Hong Seok Choi, Seoul, KR;

Hyungrok Do, Seoul, KR;

Deog-Kyoon Jeong, Seoul, KR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4074 (2006.01); G11C 11/4091 (2006.01); G11C 13/00 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4087 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0033 (2013.01); G11C 7/062 (2013.01); G11C 13/0061 (2013.01);
Abstract

A semiconductor memory device includes a bitline driver configured to drive a global bitline; a memory cell array including a first memory cell that is coupled between a cell wordline and a cell bitline; a bitline decoder including a bitline switch that couples the global bitline and the cell bitline; a wordline decoder including a wordline switch that couples a global wordline and the cell wordline; a sense amplifier configured to output a sensing signal corresponding to a state of the first memory cell based on a voltage of the global bitline; and a control circuit configured to control the bitline driver, the bitline decoder, the wordline decoder and the sense amplifier during a first read operation for the first memory cell.


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