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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11087067 B1

PDFFull Text
Date of Patent:
Aug. 10, 2021

Filed:

Jan. 06, 2021

Systems and methods for implementing tile-level predication within a machine perception and dense algorithm integrated circuit

Applicant:

Quadric.io, Inc., Burlingame, CA (US);

Inventors:

Nigel Drego, Burlingame, CA (US);

Mrinalini Ravichandran, Burlingame, CA (US);

Aman Sikka, Burlingame, CA (US);

Daniel Firu, Burlingame, CA (US);

Veerbhan Kheterpal, Burlingame, CA (US);

Assignee:

quadric.io, Inc., Burlingame, CA (US);

Attorneys:

Padowithz Alce

Alce PLLC

Primary Examiner:

Leigh M Garbowski

Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 30/27 (2020.01); G06F 30/32 (2020.01); G06F 115/10 (2020.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/27 (2020.01); G06F 30/32 (2020.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 15/8007 (2013.01); G06F 2115/10 (2020.01);
Abstract

Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.

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