The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Oct. 31, 2019
Applicant:

Seagate Technology Llc, Cupertino, CA (US);

Inventors:

Mehmet Emin Aklik, Edina, MN (US);

Antoine Khoueir, Apple Valley, MN (US);

Ara Patapoutian, Hopkinton, MA (US);

Colin Hill, Colorado Springs, CO (US);

Kurt Walter Getreuer, Colorado Springs, CO (US);

Darshana H. Mehta, Shakopee, MN (US);

Assignee:

Seagate Technology LLC, Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); H03M 13/11 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); H03M 13/1102 (2013.01);
Abstract

Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.


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