The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

May. 05, 2020
Applicant:

Skyworks Solutions, Inc., Irvine, CA (US);

Inventor:
Assignee:

Skyworks Solutions, Inc., Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/22 (2006.01); H03F 1/02 (2006.01); H03F 3/24 (2006.01); H03F 1/56 (2006.01); H03F 3/195 (2006.01); H03F 3/213 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0216 (2013.01); H03F 1/0227 (2013.01); H03F 1/0266 (2013.01); H03F 1/56 (2013.01); H03F 3/195 (2013.01); H03F 3/213 (2013.01); H03F 3/245 (2013.01); H03F 2200/222 (2013.01); H03F 2200/294 (2013.01); H03F 2200/312 (2013.01); H03F 2200/336 (2013.01); H03F 2200/387 (2013.01); H03F 2200/411 (2013.01); H03F 2200/451 (2013.01);
Abstract

Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode.


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