The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Jun. 29, 2018
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Roman Lutchyn, Santa Barbara, CA (US);

Michael Freedman, Santa Barbara, CA (US);

Andrey Antipov, Santa Barbara, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 39/10 (2006.01); H01L 39/12 (2006.01); H01L 39/24 (2006.01); H03K 3/38 (2006.01); H01L 39/16 (2006.01); G06N 10/00 (2019.01); H01L 39/22 (2006.01); B82Y 10/00 (2011.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 39/10 (2013.01); B82Y 10/00 (2013.01); G06N 10/00 (2019.01); H01L 29/0673 (2013.01); H01L 29/66977 (2013.01); H01L 39/12 (2013.01); H01L 39/16 (2013.01); H01L 39/228 (2013.01); H01L 39/24 (2013.01); H03K 3/38 (2013.01); H01L 29/20 (2013.01);
Abstract

Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.


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