The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Jan. 24, 2020
Applicant:

Murata Manufacturing Co., Ltd., Kyoto-fu, JP;

Inventors:

Atsushi Kurokawa, Nagaokakyo, JP;

Kazuya Kobayashi, Nagaokakyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/732 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 23/00 (2006.01); H01L 29/205 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/732 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 29/0817 (2013.01); H01L 29/0821 (2013.01); H01L 29/1004 (2013.01); H01L 29/205 (2013.01); H01L 29/41708 (2013.01); H01L 29/452 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2924/014 (2013.01); H01L 2924/13051 (2013.01);
Abstract

A semiconductor element includes a semiconductor substrate; a collector layer on the semiconductor substrate; a base layer on the collector layer; an emitter layer on the base layer; emitter wiring electrically coupled to the emitter layer; a top metal layer on the emitter wiring; a first protective film covering the emitter wiring and the top metal layer, the first protective film having a first opening that overlaps at least the collector layer; and a bump including an under-bump metal layer electrically coupled to the emitter wiring via the first opening, the under-bump metal layer being larger than the first opening in plan-view area. The first protective film has an inner edge around the first opening, and the inner edge is on the top metal layer.


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