logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11081469 B1

PDFFull Text
Date of Patent:
Aug. 03, 2021

Filed:

Sep. 24, 2019

Three-dimensional integrated circuit test and improved thermal dissipation

Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Saurabh Pijuskumar Sinha, San Antonio, TX (US);

Joel Thornton Irby, Austin, TX (US);

Supreet Jeloka, Austin, TX (US);

Assignee:

ARM LIMITED, Cambridge, GB;

Attorney:

Talem IP Law, LLP

Primary Examiner:

Hoai V Pham

Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 25/065 (2006.01); H01L 21/66 (2006.01); H01L 25/00 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/4871 (2013.01); H01L 22/14 (2013.01); H01L 23/367 (2013.01); H01L 24/08 (2013.01); H01L 24/89 (2013.01); H01L 25/50 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80001 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06589 (2013.01);
Abstract

A three-dimensional (3D) integrated circuit (IC) can include a bottom tier with first circuitry and first backside TSVs coupled to a substrate; a top tier coupled to the first tier at a front side and having second circuitry and second backside TSVs; and a heat conductor on the second backside TSVs of the top tier. The heat conductor is coupled to the second backside TSVs to provide improved heat dissipation through the top tier. During pre-bond testing, the top tier can be tested at speed using the second backside TSVs.

Find Patent Forward Citations

Sinha, Saurabh. (2021). Three-dimensional integrated circuit test and improved thermal dissipation (U.S. Patent No. 11081469). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11081469

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…