The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2021
Filed:
Sep. 14, 2020
Samsung Electronics Co., Ltd., Suwon-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
Provided are a non-volatile memory device and an erasing method thereof. The non-volatile memory device including a memory cell region includes first metal pads and a memory block, the memory block being disposed in a memory cell region and includes a plurality of cell strings having a plurality of memory cells stacked in a direction perpendicular to a substrate between a plurality of bit line and a common source line of the memory block, and a peripheral circuit region including second metal pads and a control logic, and vertically connected to the memory cell region by the first metal pads and the second metal pads, wherein the control logic configured to, perform control such that a first erase voltage is provided to the plurality of bit lines and the common source line, and a first erase control voltage is provided to a plurality of first selection lines and a second selection line during a first erase period, the plurality of first selection lines being used for selecting a corresponding cell string from among the plurality of cell strings and the second selection line being disposed closest to the common source line, and perform control such that a second erase voltage is provided to the plurality of bit lines, and such that a second erase control voltage is provided to at least one first selection line among the plurality of first selection lines during a second erase period, the second erase control voltage being lower than the first erase control voltage.