The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Mar. 07, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Yossi Shapira, Shoham, IL;

Jonathan Hsieh, Poughkeepsie, NY (US);

Michael Cadigan, Jr., Poughkeepsie, NY (US);

Jane Bartik, Poughkeepsie, NY (US);

Taylor J Pritchard, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0875 (2016.01); G06F 9/50 (2006.01); G06F 9/30 (2018.01); G06F 12/12 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0875 (2013.01); G06F 9/30043 (2013.01); G06F 9/5077 (2013.01); G06F 12/12 (2013.01);
Abstract

Embodiments of the inventions are directed towards a computer-implemented methods and systems for determining an oldest logical memory address. The method includes creating an M number of miss request registers and an N number of stations in a load/store unit of the processor. In response to load requests from target instructions, a processor detects each L1 cache miss. The processor stores data related to each L1 cache miss in a respective miss request register. The data includes an age of each L1 cache miss and a portion of a logical memory address of the requested load. The processor stores the entire logical memory addresses of the requested loads in respective stations based on an age of the load requests. The processor transmits the oldest logical memory address that is stored at the stations.


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