The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2021
Filed:
Jan. 12, 2018
Apple Inc., Cupertino, CA (US);
Jeremy C. Andrus, Sunnyvale, CA (US);
John G. Dorsey, San Francisco, CA (US);
James M. Magee, Orlando, FL (US);
Daniel A. Chimene, San Francisco, CA (US);
Cyril de la Cropte de Chanterac, San Francisco, CA (US);
Bryan R. Hinch, Mountain View, CA (US);
Aditya Venkataraman, Sunnyvale, CA (US);
Andrei Dorofeev, San Jose, CA (US);
Nigel R. Gamble, San Francisco, CA (US);
Russell A. Blaine, San Carlos, CA (US);
Constantin Pistol, Cupertino, CA (US);
Apple Inc., Cupertino, CA (US);
Abstract
Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.