The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Sep. 05, 2019
Applicant:

Ubilite, Inc., Carlsbad, CA (US);

Inventors:

Ismail Lakkis, Carlsbad, CA (US);

Lai Xu, San Diego, CA (US);

Assignee:

UBILITE, INC., San Diego, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/3296 (2019.01); G06F 1/3212 (2019.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/3212 (2013.01); G06F 9/4418 (2013.01);
Abstract

A radio module, radio module, comprising a battery; and a radio circuit, the radio circuit comprising: a DC-to-DC converter coupled with the batters and configured to convert a battery voltage to a first DC voltage level; at least one regulator coupled with the DC-to-DC converter and configured to covert the first DC voltage level to a second DC voltage level; a plurality of circuit blocks coupled with the at least one regulator such that the second DC voltage level is configured to provide power to the plurality of circuit blocks; a real time clock configured to provide a clock signal to the plurality of circuit blocks; and a management unit coupled with the plurality of circuit blocks and configured to implement a state machine to control the plurality of circuit blocks, wherein the state machine causes the management unit to cause the second DC voltage level to be applied to and removed from at least some of the plurality of circuit blocks during various states comprising the state machine, wherein the plurality of circuit blocks comprise a real time clock and a retention memory configured to store register values and component values for the plurality of circuit blocks, and wherein the management unit comprises a wake up logic circuit, the state machine comprising a lower power state in which only the wake up logic circuit, real time clock, and retention memory are on.


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