The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Oct. 10, 2019
Applicant:

Nvidia Corporation, San Jose, CA (US);

Inventors:

Anitha Kalva, San Jose, CA (US);

Jue Wu, Los Gatos, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3187 (2006.01); G01R 31/3177 (2006.01); G06F 13/16 (2006.01); G06Q 10/08 (2012.01); G11C 29/16 (2006.01); G01R 31/319 (2006.01); G11C 29/26 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3187 (2013.01); G01R 31/3177 (2013.01); G01R 31/31917 (2013.01); G06F 13/1668 (2013.01); G06Q 10/087 (2013.01); G11C 29/16 (2013.01); G11C 2029/2602 (2013.01);
Abstract

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.


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