The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Nov. 25, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Franco Motika, Hopewell Junction, NY (US);

Mary P. Kusko, Hopewell Junction, NY (US);

Eugene Atwood, Housatonic, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/3177 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/3172 (2013.01); G01R 31/31723 (2013.01); G01R 31/31724 (2013.01);
Abstract

An approach for testing, including a self-test method, a semiconductor chip is disclosed. The approach generates test patterns, including weighted random test patterns, for testing random pattern resistant faults, and un-modeled faults directed at specific logic groups, where the dynamically generated test pattern weights are configured to optimize test coverage and test time. The dynamically generated test patterns are based on factors related to random pattern resistant logic structures interconnected via scan chains. More particularly, the dynamically generated test patterns are designed to enable fault detection within logic structures that are resistant to fault detection when tested with random patterns.


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