The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Oct. 29, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Andrew Dow, Edinburgh, GB;

Richard L. Walke, Edinburgh, GB;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/11 (2006.01); H03M 13/07 (2006.01);
U.S. Cl.
CPC ...
H03M 13/116 (2013.01); H03M 13/07 (2013.01); H03M 13/1105 (2013.01); H03M 13/1177 (2013.01); H03M 13/1182 (2013.01);
Abstract

A decoder circuit includes an input to receive a first codeword encoded based on a quasi-cyclic low-density parity-check (QC LDPC) code. The first codeword includes a sequence of data arranged according to an order of columns in a first parity-check matrix associated with the QC LDPC code. A codeword reordering stage generates a reordered codeword by changing the sequence of the data in the first codeword based at least in part on a size of one or more circulant submatrices in the first parity-check matrix. An LDPC decoder generates a decoded codeword by decoding the reordered codeword based on a second parity-check matrix associated with the QC LDPC code. In some implementations, the second parity-check matrix may comprise a plurality of second circulant submatrices of a different size than the first circulant submatrices.


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