The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Dec. 14, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Kwanyong Lim, San Diego, CA (US);

Youn Sung Choi, San Diego, CA (US);

Ukjin Roh, San Diego, CA (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 29/0611 (2013.01); H01L 29/0847 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

Certain aspects of the present disclosure provide a structure for source or drain in a fin field-effect transistors (finFET) to increase a breakdown voltage between adjacent finFETs in a semiconductor device. One example semiconductor device generally includes a plurality of finFETs, each of the finFETs comprising a source and a drain, wherein at least the source or the drain in at least one finFET of the plurality of finFETs has a profile with at least one rounded tip to increase a breakdown voltage between the at least one finFET and an adjacent finFET in the plurality of finFETs.


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