The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Jul. 03, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Fumitaka Arai, Yokkaichi Mie, JP;

Keiji Hosotani, Yokkaichi Mie, JP;

Nobuyuki Momo, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); H01L 27/11524 (2017.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01); H01L 27/11519 (2017.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: first to fifth interconnects; a semiconductor layer having one end located between the fourth interconnect and the fifth interconnect and other end connected to the first interconnect; a memory cell; a conductive layer having one end connected to the second interconnect and other end connected to the semiconductor layer; a first insulating layer provided to extend between the third and fourth interconnects and the semiconductor layer, and between the fifth interconnect and the conductive layer; an oxide semiconductor layer provided to extend between the fourth and fifth interconnects and the first insulating layer; and a second insulating layer provided to extend between the fourth and fifth interconnects and the oxide semiconductor layer.


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