The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Mar. 26, 2020
Applicant:

Sharp Kabushiki Kaisha, Osaka, JP;

Inventors:

Tong Lu, Oxford, GB;

Michael James Brownlow, Oxford, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/325 (2016.01); G09G 3/3258 (2016.01); G09G 3/36 (2006.01); G09G 3/3291 (2016.01);
U.S. Cl.
CPC ...
G09G 3/325 (2013.01); G09G 3/3258 (2013.01); G09G 3/3291 (2013.01); G09G 3/3659 (2013.01); G09G 2300/0852 (2013.01);
Abstract

A pixel circuit compensates the threshold voltage variations of the drive transistor with an ultra-short one horizontal (1H) time, with additionally removing the possible memory effects associated with the light-emitting device and the drive transistor from the previous frame. An ultra-short 1H time (<2 μs) is achieved via separation of threshold compensation of the drive transistor and data programming phases. The pixel circuit has a two-capacitor configuration, whereby a first capacitor is used for drive transistor threshold compensation, and a second capacitor is used to store the data voltage during a data pre-loading phase. Two transistors are employed to electrically connect the gate of the drive transistor to the second capacitor that stores the data voltage, wherein each transistor in this dual transistor configuration is controlled by a different control signal. A timing sequence of the different control signals is used to ensure that a mid node of the dual transistor configuration is refreshed before the data is applied to the gate of the drive transistor. An array of individual pixel circuits is controlled using a global compensation scheme in which global control signals are applied to the individual pixel circuits of the pixel array.


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