Digital circuits for radically reduced power and improved timing performance on advanced semiconductor manufacturing processes

Abstract

Disclosed is a resonant circuit and method for matched clock and data timing performance for improving timing closure of digital circuits on advanced semiconductor manufacturing processes. The matched resonance circuit comprises pulse generator circuit () and plurality of generating latches (A-N) and plurality of sampling latches (A-N). The pulse generator circuit () comprises plurality of inverters (A-N), optimum resistance () and exclusive OR (Ex-OR) gate () which are connected in series and a matched capacitance. The pulse generator circuit () generates timing pulse output using one or more buffers and clock inductor. Each generating latch receives clock timing pulse output as timing pulse into plurality of sampling flip-flop latches (A-N) through clock sample path (CS) to match arrival of timing pulse and outputs of plurality of input data lines that are resonated by connecting one or more of respective load capacitances with at least one shared inductor ().