The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2021
Filed:
Sep. 30, 2020
Nxp B.v., Eindhoven, NL;
Domenico Liberti, San Jose, CA (US);
Andre Gunther, San Jose, CA (US);
Jeffrey Alan Goswick, Phoenix, AZ (US);
NXP B.V., San Jose, CA (US);
Abstract
A power supply switching circuit () and methodology are disclosed for connecting the greater of first and second power supplies (V, V) to an output voltage node (V) with a comparator (), active power supply switching circuit (), gate driver circuit (), and switching array (SW-SW) to generate control signals for a pair of PMOS power switches (MP, MP) by remapping first and second voltage supplies (V, V) to bias the n-wells of the PMOS power switches while simultaneously driving the gate terminals of the PMOS power switches with the gate driver circuit () only in response to a comparator activation signal by generating overlapping phase signals (PHI_, PHI_) which controls timing of first and second power supply selection signals so that a ground voltage is supplied as the first power supply selection signal only after the maximum bias voltage is supplied as the second power supply selection signal.