The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2021
Filed:
Aug. 22, 2018
Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;
Yukinori Shima, Tatebayashi, JP;
Masataka Nakada, Tochigi, JP;
Masayoshi Dobashi, Shimotsuga, JP;
Kenichi Okazaki, Tochigi, JP;
Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken, JP;
Abstract
A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first conductive layer, and a second conductive layer. The second semiconductor layer is positioned over the first semiconductor layer, the second conductive layer is positioned on the second semiconductor layer, and the second insulating layer is provided so as to cover a top surface and a side surface of the second conductive layer. The second conductive layer and the second insulating layer include a first opening, and the third semiconductor layer is provided in contact with a top surface of the second insulating layer, a side surface of the first opening, and the second semiconductor layer. The first insulating layer is positioned between the first conductive layer and the third semiconductor layer, the third insulating layer is positioned between the first insulating layer and the first conductive layer, and the fourth insulating layer is provided so as to surround the first conductive layer.