The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2021

Filed:

Aug. 29, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventor:

Hiroyasu Sato, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/11582 (2017.01); H01L 29/10 (2006.01); H01L 29/167 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 27/11519 (2017.01); H01L 29/792 (2006.01); H01L 29/788 (2006.01); H01L 27/11565 (2017.01); H01L 27/11556 (2017.01); H01L 21/28 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/26513 (2013.01); H01L 21/31116 (2013.01); H01L 21/324 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 29/105 (2013.01); H01L 29/1037 (2013.01); H01L 29/167 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/7883 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); H01L 21/02592 (2013.01); H01L 21/02595 (2013.01); H01L 21/02667 (2013.01); H01L 21/31053 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a substrate, a stack comprising a plurality of conductive layers stacked one over the other in a first direction, and an insulating layer interposed between adjacent conductive layers located over the substrate, a first semiconductor layer extending inwardly of the stack and through the plurality of conductive layers in the first direction, a memory layer located between the first semiconductor layer and the plurality of conductive layers, and a second semiconductor layer located over, and in contact with, the first semiconductor layer, wherein the second semiconductor layer includes a third semiconductor layer containing phosphorous, and a fourth semiconductor layer containing carbon provided between the first semiconductor layer and the third semiconductor layer.


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