The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2021

Filed:

Sep. 15, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Thomas D. Bonifield, Dallas, TX (US);

Jeffrey A. West, Dallas, TX (US);

Byron Williams, Plano, TX (US);

Honglin Guo, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 23/00 (2006.01); H01L 23/58 (2006.01); H01L 23/31 (2006.01); H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/3171 (2013.01); H01L 23/585 (2013.01); H01L 23/62 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/48471 (2013.01); H01L 2224/48479 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/3862 (2013.01);
Abstract

A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.


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