The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2021

Filed:

Dec. 19, 2018
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Soon-Dong Cho, Gumi-si, KR;

Jung-Jae Kim, Goyang-si, KR;

Sang-Uk Lee, Seoul, KR;

Hyung-Jin Choe, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/3275 (2016.01); G09G 3/36 (2006.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3275 (2013.01); G09G 3/20 (2013.01); G09G 3/3685 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0673 (2013.01); G09G 2330/021 (2013.01);
Abstract

A display device can include a gate driver configured to drive gate lines of a panel; a data driver configured to drive data lines of the panel; a timing controller configured to control operations of the gate driver and the data driver; and a level shifter integrated circuit (IC) configured to receive a plurality of control signals from the timing controller, and generate and output a plurality gate control signals for controlling driving of the gate driver, in which the plurality of control signals include an on clock and an off clock, and the level shifter IC stores the on clock and the off clock in buffers based on one or more control signals from the timing controller, generates a plurality of scan clocks by logically processing the on clock and the off clock, and outputs the plurality of scan clocks to the gate driver.


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