The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

Jul. 16, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Pranshu Kalra, Bangalore, IN;

Srikanth Srinivasan, Bangalore, IN;

Devraj Rajagopal, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); H03K 5/01 (2006.01); H03K 19/20 (2006.01); H03K 19/0175 (2006.01); H03K 19/0185 (2006.01); H03K 17/06 (2006.01);
U.S. Cl.
CPC ...
H03K 5/01 (2013.01); H03K 17/063 (2013.01); H03K 17/687 (2013.01); H03K 19/0175 (2013.01); H03K 19/0185 (2013.01); H03K 19/20 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01);
Abstract

A receiver includes a low-side buffer having an input terminal coupled to receive an input signal and having an output terminal coupled to a buffer terminal. Responsive to the input signal being LOW, the low-side buffer is configured to couple the buffer terminal to ground. The receiver also includes a high-side buffer having an input terminal coupled to receive the input signal and having an output terminal coupled to the buffer terminal. Responsive to the input signal being HIGH, the high-side buffer is configured to provide an I/O voltage at the buffer terminal. The receiver also includes an output stage coupled to the buffer terminal and having a low voltage terminal configured to receive a low supply voltage. The output stage is configured to provide an output signal responsive to the I/O voltage at the buffer terminal, wherein the output signal is lower than the I/O voltage.


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