The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

Dec. 20, 2013
Applicants:

Aledia, Grenoble, FR;

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Eric Pourquier, Grenoble, FR;

Hubert Bono, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/06 (2010.01); H01L 33/18 (2010.01); H01L 33/00 (2010.01); H01L 33/48 (2010.01); H01L 33/42 (2010.01); H01L 27/115 (2017.01); H01L 33/08 (2010.01); H01L 33/24 (2010.01); H01L 29/06 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/12 (2006.01); H01L 33/16 (2010.01); H01L 33/02 (2010.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 33/06 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 21/02603 (2013.01); H01L 27/115 (2013.01); H01L 29/068 (2013.01); H01L 29/0676 (2013.01); H01L 29/125 (2013.01); H01L 29/127 (2013.01); H01L 29/66469 (2013.01); H01L 33/007 (2013.01); H01L 33/0008 (2013.01); H01L 33/0062 (2013.01); H01L 33/0095 (2013.01); H01L 33/02 (2013.01); H01L 33/08 (2013.01); H01L 33/16 (2013.01); H01L 33/18 (2013.01); H01L 33/24 (2013.01); H01L 33/42 (2013.01); H01L 33/48 (2013.01); H01L 29/6609 (2013.01); H01L 2924/0002 (2013.01); H01L 2933/0016 (2013.01);
Abstract

A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.


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