The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 2021
Filed:
Jul. 31, 2019
Qorvo Us, Inc., Greensboro, NC (US);
Julio C. Costa, Oak Ridge, NC (US);
Robert Aigner, Ocoee, FL (US);
Gernot Fattinger, Sorrento, FL (US);
Dirk Robert Walter Leipold, San Jose, CA (US);
George Maxim, Saratoga, CA (US);
Baker Scott, San Jose, CA (US);
Merrill Albert Hatcher, Jr., Greensboro, NC (US);
Jon Chadwick, Greensboro, NC (US);
Qorvo US, Inc., Greensboro, NC (US);
Abstract
The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.