The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

Sep. 24, 2019
Applicant:

Yi-hui Lee, Taichung, TW;

Inventor:

Yi-Hui Lee, Taichung, TW;

Assignee:

Other;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/76224 (2013.01); H01L 23/3185 (2013.01); H01L 23/49575 (2013.01); H01L 24/27 (2013.01); H01L 24/32 (2013.01); H01L 24/96 (2013.01); H01L 29/401 (2013.01); H01L 2224/32245 (2013.01);
Abstract

The present invention relates to a method of manufacturing a power device and a structure of the power device, which is used to solve the problem that conventional power device needs to be independently packaged and requires a welding process. The method includes: forming a plurality of semiconductor device layers spaced in intervals on a front of a silicon wafer; excavating a plurality of grooves on the front of the silicon wafer to separate the plurality of semiconductor device layers; filling each of the plurality of grooves with each of a plurality of first spacer materials; grinding a back of the silicon wafer until the first spacer materials being exposed; attaching a plurality of metal layers to a region of the back of the silicon wafer opposite to the plurality of semiconductor device layers; and electrically connecting each of independent plurality of lead frames to the plurality of metal layers respectively. The present invention further includes the structure of the power device.


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Lee, Yi-Hui. (2021). Method of manufacturing power device with improved the utilization rate of wafer area (U.S. Patent No. 11062949). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11062949

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