The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11061701 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 13, 2021

Filed:

Sep. 25, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Michael J. Becht, Poughkeepsie, NY (US);

Raymond Wong, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 9/455 (2018.01); G06F 30/34 (2020.01); G06F 30/331 (2020.01); G06F 30/33 (2020.01); G06F 30/3308 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 9/45508 (2013.01); G06F 1/08 (2013.01); G06F 9/455 (2013.01); G06F 30/33 (2020.01); G06F 30/331 (2020.01); G06F 30/3308 (2020.01); G06F 30/34 (2020.01); G06F 2119/12 (2020.01);
Abstract

Examples of techniques for emulating an application-specific integrated circuit (ASIC) array using a field programmable gate array (FPGA) are disclosed. In one example implementation according to aspects of the present disclosure, a method may include loading configuration information to the FPGA, wherein the configuration information is representative of configuration information of the ASIC. The method may further include emulating the ASIC using the FPGA loaded with the configuration information by applying a fast emulation clock signal to the FPGA. The fast emulation clock signal is a multiple of a system clock signal.


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